High-Power Wideband L-Band Suboptimum Class-E Power Amplifier

I. Introduction

HIGH-EFFICIENCY power-amplification techniques provide important advantages for RF and microwave systems and circuits in general, but especially in high-power or battery-powered applications. The ability of switchmode high-efficiency power amplifiers to minimize power consumption, temperature, size, and weight of radio transmitters is well known; however, in practice, it is difficult to make use of high-efficiency switchmode amplification techniques in scenarios involving high power levels and high frequencies due to device intrinsic capacitances and switching times, package parasitics, etc. Therefore, choosing a class of operation capable of dealing with such nonidealities is crucial to achieve the benefits of high-efficiency amplification at high frequencies.

Among high-efficiency switchmode amplification classes, Class-E is known for being tolerant to transistor switching imperfections. It also requires simple load impedance profiles that can be successfully synthetized both in narrowband and wideband conditions by using simple load networks [1].

The equivalent intrinsic output capacitance (C_OUT) of RF and microwave transistors imposes a limit to the maximum operating frequency of a nominal Class-E amplifier (f_max) that has been investigated by several authors [2]-[7]. In practice, f_max of state-of-the-art solid-state technologies is often insufficient to cover some of the most important RF and microwave power applications. This means that using present day commercially available transistors, nominal Class-E amplifiers still cannot be built for many popular and important communications and industrial applications. Suboptimum Class-E operation can be a solution for those cases. Suboptimum Class-E retains most of the benefits of nominal Class-E beyond f_max, but tolerates higher C_OUT figures [8]. This means that suboptimum Class-E can operate with transistors exhibiting higher C_OUT than the maximum allowed for nominal Class-E operation (C_OUTmax) while experiencing tolerable drain efficiency degradation with respect to nominal Class-E. In addition, the load requirements for suboptimum Class-E above f_max, both at fundamental and harmonics, are similar to the load requirements for nominal Class-E. Therefore, the load networks required to build nominal Class-E amplifiers can be easily adapted to suboptimum Class-E amplifiers.

Even though suboptimum Class-E cannot provide 100% drain efficiency (ηD) above f_max, it can match the performance of other high-efficiency amplification classes such as Class-F or Class-F^-1, with the advantage of requiring simpler load networks that can be designed for broadband operation. Other important aspects regarding suboptimum Class-E operation above f_max are that its inherent drain-to-source peak to average voltage ratio (V_DSpeak/V_DD) is lower than the V_DSpeak/V_DD ratio of nominal Class-E, and that its power-output capability (P_max) is also slightly higher [9].

For all these reasons, suboptimum Class-E is a feasible alter-native for high-efficiency amplification in scenarios involving wideband operation, high power levels, high frequencies, and packaged transistors.

Gallium-nitride (GaN) transistors exhibit important advantages in switchmode amplifiers in the microwave region compared to other semiconductor technologies. The high breakdown voltage of GaN transistors is more suitable than other solid-state technologies (such as GaAs, etc.) for switchmode amplification classes, such as Class-E due to their high peak voltage requirements. Moreover, high breakdown voltage power GaN transistors typically require high load impedances, which contribute to simplify the impedance transformation networks. Moreover, these networks can be designed for low losses, thus increasing the overall efficiency of the amplifier.

In this paper, a novel wideband high-power suboptimum Class-E power amplifier for L-band is proposed. It can operate in both continuous wave (CW) and pulsed modes providing up to 180 W of output power (P_OUT) from 900 to 1500 MHz. It exhibits peak drain efficiency (ηD_peak) up to 85%, power gain (G_P) up to 14.7 dB, and power-added efficiency (PAE) up to 81%. It covers the most important RADAR sub-bands in the L-band in all operation modes without need for adjustment. Furthermore, it does not require any gain compensation circuit when used in pulsed RADAR applications. To the best of the authors' knowledge, the proposed amplifier offers superior performance than conventional L-band amplifiers with similar output power levels.

The amplifier uses a double-cell packaged unmatched GaN HEMT (CGH4018OPP from Wolfspeed, Inc). Its load network has been designed using the load admittance synthesis technique to provide the value required by the transistor at fundamental and harmonics to operate in suboptimum Class-E over almost one octave. The load network design is based on the double reactance compensation circuit [10], [11], but it also accomplishes impedance transformation functions. The network comprises device capacitance C_OUT, package parasitics, and an external circuit including microstrip transmission lines and lumped capacitors.

The input network of the amplifier has been designed to ensure that the transistor switches over its entire bandwidth using constant driving power (P_IN); this has been achieved by pro-viding constant and maximum voltage gain (G_V) from the 50-Ω input port of the amplifier to the equivalent input capacitance of the transistor (C_IN). Once again, the input network comprises device input capacitance GIN, package parasitics, and an external circuit that includes lumped components and microstrip transmission lines. The complexity of both load and input networks of the amplifier has been minimized to keep their power losses as low as possible without degrading η_D and PAE. Their simple design also contributes to ease their construction and repeatability, reducing the impact of manufacturing tolerances. This is an important practical benefit when combining several amplifiers to achieve high output power levels.

II. Amplifier Description

The amplifier uses a high-power packaged (without internal matching) GaN HEMT; this feature is crucial for the design of the amplifier, as it will be shown in the following sections that the intrinsic capacitances of the device and the package poro-sities are relevant parts of the load and input networks. Three major parts and subnetworks can be distinguished in this amplifier, as shown in Fig. 1: transistor (including die and package), load network, and input network. Sections II-A~II-H describe the different subnetworks shown in Fig. 1.

A. Transistor
The high breakdown voltage of the transistor used in this amplifier (V_BR = 120 V) suggests safe operation for this de-vice in nominal Class-E at power supply voltages (V_DD) as high as 28 V. However, prior to any further considerations, it is necessary to determine if the operating frequency of the amplifier is above or below the f_max, allowed by the transistor. f_max can be calculated from the transistor C_OUT, its maximum drain current (I_Dmax) and V_DD [11]. According to the manufacturer of the CGH4018OPP, C_DS = 9.6 pF @ 28 V/1 MHz and C_GD = 1.6 pF @ 28 V/1 MHz (per transistor cell). Its minimum saturated drain current is I_DSmin = 23 A. These factors can be rearranged to calculate f_max from C_OUT and P_OUT in nominal Class-E conditions as follows:

Fig. 2 shows f_max for the CGH4018OPP at different P_OUT and V_DD levels. Considering that P_OUT = 90 W is a safe output power level for the CGH4018OPP (per cell), from Fig. 2, f_max ≈ 818 MHz at VDD = 28 V. This frequency is clearly lower than the lower end of the target frequency band. Fig. 2 also suggests that f_max could be traded for P_OUT or V_DD, but this solution involves increasing the peak drain current (I_Dpeak), and thus, decreasing the load impedance required by the transistor.

The model of the transistor provided by its manufacturer is a compiled one that also includes the effects of its package and it does not show the value of the components of the equivalent circuit of the transistor required for the design of the amplifier. Therefore, the model shown in Fig. 3 proposed by Sokol and Redl for transistors in switchmode operation [12] was used to find several parameters and equivalent circuit elements of the amplifier. The values obtained are shown in Table I; for simplicity, they are considered linear.

TABLE I: CGH40180PP SIMPLIFIED MODEL FOR SWITCHMODE OPERATION

B. Class of Operation
The f_max provided by the CGH4018OPP is below the lower end of the L-band for the target P_OUT and V_DD; nevertheless, the transistor still can operate safely in suboptimum Class-E at frequencies above f_max with very good performance. It can also achieve ηD similar to those achieved by other high-efficiency amplification classes such as Class-F or Class-F^-1, but with the advantage of requiring a simpler load network that contributes to improve the power efficiency of the amplifier.

In [9] and [13]-[15], it is shown that the maximum achievable drain efficiency (ηD_max) for suboptimum Class-E is 97% at 1.56 f_max and 92% at 2 f_max. In addition, V_DSpeak/V_DD decreases down to 3.077 at 1.56 f_max, and 2.677 at 2f_max; note that V_Dspeak /V_DD = 3.56 for nominal Class-E operation. These figures are similar to those obtained with other high-efficiency operation classes such as Class-F [16]-[18].

Similar to nominal Class-E, suboptimum Class-E operation above f_max requires a complex load at fundamental and pure ca-pacitive load at harmonics, being the phase angle of the load admittance at fundamental the main difference between the loads required by suboptimum Class-E and nominal Class-E. From [9], the optimum load value that maximizes the drain efficiency of an amplifier operating in suboptimum Class-E above f_max can be obtained. The angle of the optimum load required for suboptimum Class-E operation is shown in Table II for an ideal (lossless) transistor with zero switching times. The following two conclusions can be drawn from Table II.

• There is an optimum load angle at fundamental for the sub-optimum Class-E amplifier that maximizes its drain efficiency. This optimum load angle depends on the f / f_max ratio.

TABLE II: OPTIMUM LOAD ANGLE FOR SUBOPTIMUM CLASS-E VERSUS F / F_max

• The load admittance versus frequency profiles required by nominal and suboptimum Class-E amplifiers are similar. Therefore, the load network used for nominal Class-E amplifiers can also be easily adapted for suboptimum Class-E operation.

C. Load Network
This amplifier was designed using the load impedance synthesis technique [19]; this means that the load required for suboptimum Class-E operation at fundamental and harmonics was synthesized and presented to the equivalent "switch" that models the transistor (SW in Fig. 3). This load depends on the reactance of C_OUT(X_COUT) at the highest operating frequency of the amplifier (X_COUT@1500 MHz), the power supply voltage (V_DD = 28 V), and the output power level of the amplifier (P_OUT= 90 W). The load required by the amplifier can be approximately obtained from [9] and [20] considering all the factors mentioned before. For this amplifier, the load admittance at the fundamental frequency has been chosen to be Y_L(f₀) = 0.1 S (-25°) at the center of the band (the load admittance angle at fundamental varies from -30° to -23° over the band of the amplifier) and the load admittance angle at harmonics to be 90°; these values were then adjusted using harmonic balance optimization over the entire amplifier bandwidth to achieve the desired output power and efficiency goals. This load admittance is presented to the switch SW over the complete bandwidth by means of a load network that trans-forms the 50-Ω impedance of the output port of the amplifier into the required admittance value.

The load network used in this amplifier is shown in Fig. 4. It is a double reactance compensation circuit that also provides impedance transformation functions and a port for dc voltage injection. Table III shows the values of the elements of the load network.

TABLE III: ELEMENTS OF THE LOAD NETWORK OF THE AMPLIFIER
Load network component values

Three load planes marked as LP₁, LP₂, and LP₃ are shown in the schematic of Fig. 4: LP₁ is a virtual load plane located just at the equivalent switch SW that models the transistor. The load required for suboptimum Class-E operation of the amplifier must be provided at this load plane. LP₂ is the actual drain-to-source load plane at the output of the transistor package, where load measurements can be carried out. LP₃ is the 50-Ω load plane at the output of the amplifier.

Three sub-networks can be identified in this load network: LN₁, LN₂, and LN₃.

• LN₁ is made up of C_OUT, the parasitics of the output port of the transistor package, L_pckgOUT and TL_pcksOUT, and two external components: a short microstrip transmission line, T_LO1, and two paralleled ceramic multilayer capacitors, C_2OA. These components are arranged as a π-type low-pass network, and thus are equivalent to a quarter-wave transmission-line transformer (in narrowband conditions).
• LN₂ is comprised by a short-circuited microstrip line that acts an inductor, TL_O2, and another lumped ceramic multi-layer capacitor, C_2OB. These components operate as a parallel resonant circuit. The short-circuited end of TL_O2 is also used as a port to inject the power supply dc voltage V_DD
• LN₃ is a microstrip quarter-wave transmission line transformer. LN₃ carries out most of the load impedance transformation of the load network, and also contributes to achieve the double reactance compensation effect by keeping the load admittance angle approximately constant over the full amplifier bandwidth. The load admittance profile Y_L(f) achieved by this load network at the virtual plane LP₁ is shown in Fig. 5. The double peak load admittance profile provided by this load network is responsible for the amplifier's double peak output power profile that will be shown later. As shown in Fig. 5, the phase and magnitude plots of the load admittance at the fundamental cannot be kept constant and parallel over the entire amplifier bandwidth; therefore, it is not possible to achieve both flat P_OUT and ηD simultaneously. In practice, it is more useful to achieve a flat P_OUT than a flat no; thereby, this amplifier was designed to provide flat P_OUT profile at the expense of a decrease of ηD at the upper end of the target frequency band.

D. Input Network
With some exceptions [21], [22], the design of optimum driving methods and input networks for RF and microwave switchmode power amplifiers has not been covered in the technical literature, even though inefficient driving of switchmode RF power amplifiers directly translates into significant power gain (G_P) losses (about 3 dB in most cases) that reduce their overall efficiency. Switchmode amplifiers using transconductance semiconductor devices, as the GaN HEMT used by the amplifier described in this paper, require a voltage waveform at the gate port capable of driving the device from "on" to "off" state, and vice-versa, with the shortest possible rise and fall times; in practice, times shorter than 30% of the switching period are considered sufficient for appropriate operation.

The trapezoidal voltage waveform is considered the most efficient waveform to drive switchmode power amplifiers [11], but device and package parasitics of most RF and microwave transistors make a trapezoidal voltage waveform very difficult to implement in practice. In the amplifier described in this work, C_IN and inductive parasitic elements of the transistor precluded the implementation of trapezoidal voltage waveforms at its gate. Thus, a sine voltage is used to drive the amplifier at the expense of decreasing G_P.

Another important feature demanded by switchmode power amplifiers is a flat G_P profile to guarantee that a constant driving power level P_IN can drive the amplifier over the entire bandwidth.

The input network of the amplifier proposed in this paper was designed to fulfill the two requirements mentioned above, while introducing minimum power losses and accounting for transistor and package parasitics. This input network is shown in Fig. 6; element values are shown in Table IV.

Three source planes SP₁, SP₂, and SP₃, are shown in Fig. 6: source plane SP₁ is a virtual plane located just at the left of the equivalent input capacitance of the transistor (C_IN) and its equivalent input resistance (r_IN). The source plane SP₂ is located at the input of the transistor package (actual input impedance measurements can be obtained at this plane). Source plane SP₃ is located at the 50-Ω input port of the amplifier.

TABLE IV: ELEMENTS OF THE LOAD NETWORK OF THE AMPLIFIER
Input network values

The input network of the amplifier is made up of three subnetworks, as shown in Fig. 6: SN₁ includes C_IN and r_IN, most significant package parasitics (L_pckglN and TL_pckgIN), and an external microstrip transmission line TL_I1 SN2 comprises a short-circuited microstrip line TL_I2, and a set of ceramic multilayer capacitors C₂. The short-circuited end of TLI2 is used to inject the required negative gate to source bias voltage for the transistor V_bias. SN₃ is a microstrip quarter-wave transmission-line transformer that carries out most of the source network impedance transformation.

This network provides flat (G_V(f)) from the input port of the amplifier SP₁ to the equivalent input capacitance of the transistor at SP₃. It provides good performance regarding input re-turn losses (IRLs) at the upper end of the amplifier bandwidth; it must be noted that the required flat G_V(f) profile from SP₃ to SP₁ is only possible at the expense of reflecting significant input driving power at the lower end of the bandwidth, and there-fore, at the expense of degrading IRL down to about -1 dB at 900 MHz. Fig. 7 shows G_V(f) from SP₃ to SP₁ and |SP₁₁| obtained with this network.

In order to achieve reasonable IRL performance, the two cells of the transistor were combined building a balanced amplifier by means of a hybrid quadrature combiner, as will be shown in Section III.

III. Amplifier Simulation, Building, and Testing

The amplifier was simulated and optimized using the harmonic balance simulator and optimizer of Microwave Office Design suite and the nonlinear model of the transistor provided by the manufacturer. In spite of the highly nonlinear nature of this simulation, it is important to point out that only minor convergence problems were found during the process. Fig. 8 shows simulated P_OUT(f) of the amplifier (for one cell of the CGH40180PP) for V_DD values ranging from 12 to 28 V. Fig. 9 shows the simulated obtained at similar conditions.

From Fig. 8, it can be observed that P_OUT(f) is flat from 900 to 1500 MHz, with a smooth double peak shape that comes from the double peak load admittance profile shown in Fig. 5, as mentioned before. Fig. 9 shows ηD(f); it decreases with frequency, but it is still high (close to 80%) at the upper end of the target bandwidth. The dependence of ηD on V_DD is moderate.

In order to test the accuracy of the simulation results, a basic manually controlled harmonic load-pull study was carried out on the transistor using a harmonic controlled load-pull test-bench [23]. The load—pull tests confirmed and validated the reasonable accuracy of the design hypothesis and the simulation results.

A prototype of the amplifier was built on 0.508-mm-thick R04350B substrate from the Rogers Corporation. The layout of the amplifier was carefully designed in order to minimize any additional parasitic elements. It was found, as expected, that the correct placement of lumped components was crucial to achieve the predicted performance. The full schematic of the amplifier is shown in Fig. 10. Fig. 11 shows a photograph of the amplifier.

Both P_OUT and ηD were measured in CW conditions using a calibrated test bench comprising a 40-dB attenuator and an N1912A Agilent power meter. The results are shown in Figs. 13 and 14 for V_DD ranging from 12 to 28 V.

The results shown in Figs. 12 and 13 were obtained by injecting constant input driving power P_IN = 36 dBm over the entire amplifier bandwidth. Simulation results shown in Figs. 8 and 9 and the measured results shown in Figs. 12 and 13 were in good agreement.

P_OUT and ηD were also measured in pulsed mode (pulse width = 1 ms, pulse repetition frequency PRF = 100 Hz). The amplifier can provide up to 94 W in pulsed mode (per cell) versus up to 90 W in CW conditions. Measured peak drain efficiency was 90% @ 28 V in pulsed operation versus 85% ( 28 V in CW conditions.

Fig. 14 shows the measured PAE for different values of V_DD. The strong dependence of the PAE on V_DD is caused by the Gp dependence on V_DD, which is a common feature of switchmode amplifiers; it ranges from G_P = 15 dB @ 28 V to G_P = 8 dB @ 12 V. Maximum PAE is achieved for V_DD = 28 V.

Fig. 15 shows P_OUT versus P_IN in CW operation for V_DD = 28 V at 1000, 1200, and 1400 MHz. Note that the amplifier can also be used below compression providing G_P about 20 dB at the expense of lower ηD.

The two cells of the CGH4018OPP were used to build two identical amplifiers that were combined into a balanced amplifier using two 3-dB 90° hybrid combiners (1E1305 from Anaren) to double the output power and to decrease input standing wave ratio (SWR) down to acceptable levels. Since P_OUT of the balanced amplifier exceeds the maximum power rating of the combiner in CW, the amplifier can only be operated at its maximum output power in pulsed mode at 50% duty cycle. Note that the amplifier is able to operate in CW mode at full power if a suitable hybrid combiner with a higher power rating was used. This happens only for V_DD higher than 20 V, corresponding to P_OUT > 100 W.

The measured output power of the hybrid amplifier (P_OUTCOMB) and its drain efficiency (η_DCOMB) operating in pulsed mode (pulse width = 1 ins, PRF = 100 Hz) are shown in Figs. 16 and 17, respectively, for VDD ranging from 12 to 28 V.

As mentioned before, one of the benefits of using a balanced amplifier topology is an important improvement of the ERL and input SWR. Fig. 18 shows the measured input SWR and |S₁₁| of the balanced amplifier.

One of the most important and promising applications for this circuit is to operate as an RF stage in an envelope elimination and restoration (EER) or envelope tracking (ET) amplifier; both V_DD - AM and V_DD PM performance need to be well characterized in this application [24]. Fig. 19 shows the measured V_DD - AM and VDD - PM at 1300 MHz. From these figures, V_DD - AM conversion appears negligible, but V_DD - PM conversion (caused by the nonlinear nature of C_OUT) would need to be corrected by predistortion to achieve reasonable linear performance in EER/ET applications [25], [26].

Fig. 20 shows a demodulated 1300-MHz pulsed RADAR signal (pulse width = 1 ins, PRF = 100 Hz, P_OUTPEAK = 180 W) that can be used to analyze the pulse operation performance of the amplifier [27]. The demodulated pulse does not show fading, and consequently, no gain compensation circuit is required.

Fig. 21 shows the measured harmonic level of the amplifier, most significant harmonics are below 30 dBc.

TABLE V: STATE-OF-THE-ART L-BAND PUBLISHED GaN POWER AMPLIFIERS

IV. Conclusion

A high-efficiency wideband high-power L-band suboptimum Class-E power amplifier based on a packaged (but unmatched) GaN HEMT has been demonstrated in this paper. It covers the main RADAR sub-bands at L-band without the need for manual adjustment, exhibiting 50% fractional bandwidth at a center operating frequency of 1200 MHz. It provides output power up to 180 W and drain efficiency in excess of 80% over almost its entire bandwidth. To the best of the authors' knowledge, the performance of this amplifier outperforms other amplifiers for the same frequency band and output power 'level, especially commercial grade ones, as shown in Table V. A simple low-loss double-reactance compensation and impedance transformation network that includes the transistor die and package parasitics provides the load admittance required by its equivalent switch to operate in suboptimum Class-E. The input network of the amplifier has been designed to provide constant G_P over the complete operation bandwidth. This amplifier can be directly used in most RADAR applications in the L-band and also as an RF base stage in EER and ET transmitters for services such as digital audio broadcasting (DAB) or mobile satellite communications. Its repeatability enables simple combination of amplifier units to achieve higher output power levels. The design principles presented in this paper can be easily applied to larger GaN devices as soon as they become available in the market, and they can also be extended for designs at higher frequency bands.

The amplifier is based on suboptimum Class-E operation, a high-efficiency amplification mode not very widely used and known. However, it has been shown that this class of operation allows a transistor to provide very high efficiency at frequencies above its maximum frequency for nominal Class-E operation, offering performances similar to other high-efficiency modes commonly used at this frequency bands (such as Class-F or Class-F^-1) and requiring a simpler load network.

Acknowledgement

The authors are grateful to Wolfspeed, Inc. for supporting the publication of this paper. The authors want to thank M. Rodriguez-Gonzalez for his great work checking this paper's manuscript.

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Francisco Javier Ortega-Gonzalez, photograph and biography not available at time of publication.

David Tena-Ramos, photograph and biography not available at time of publication.

Moises Patiiio-Gomez, photograph and biography not available at time of publication.

Jose Manuel Pardo-Martin, photograph and biography not available at time of publication.

Diego Maduelio-Pulido, photograph and biography not available at time of publication.

Manuscript received May 18, 2013; revised August 05, 2013; accepted August 06, 2013. Date of publication September 05, 2013; date of current version October 02, 2013.

F. J. Ortega-Gonzalez, D. Tena-Ramos, M. Patiño-Gomez, and J. M. Pardo-Martin are with EUIT de Telecomunicacion, Centro de Electronica Indutrial, Grupo de Ingenieria de Radio, Universidad Politecnica de Madrid, 28031 Madrid, Spain (e-mail: fjortega@diac.upm.es).

D. Madueño-Pulido is with Indra Sistemas, 28850 Torrejón de Ardoz, Spain. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2013.2279366

Copyright © 2013.
Reprinted from IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 10, OCTOBER 2013

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