A radar system designer’s most coveted objectives are achieving a long range, adequate resolution to distinguish objects in close proximity to each other, and the ability to not only determine target velocities but target types in order to help differentiate friendlies from adversaries.
Much that goes into achieving these goals relies on the basic radar equation below:
Where:
Given the importance of power to the radar range, engineers may focus entirely on squeezing as much power as possible within space constraints — reaching the highest power density possible by using Wolfspeed’s latest GaN technologies. On the other hand, to allow for radar algorithms to distinguish various objects, others may sacrifice power for a “clean” pulse.
A combination of both approaches is essential, and engineers can design for peak power points of the load-pull simulation while also paying attention to other parts of the circuit for baseband signal fidelity.
Figure 1: An ideal pulse envelope (top). Distortions in a real-world RF pulse (bottom) affect radar performance.
The importance of pulse fidelity
The pulse radar transmitter sends out an RF carrier for the duration of the pulse. The wave is reflected by the target back to the receiver. Signal processing then helps evaluate the nature of the return signal to determine target characteristics.
Real-world pulses are usually not the textbook idealizations with flat tops and zero rise and fall times against a noiseless background. To understand how pulse fidelity affects radar performance, we must start by understanding that typical pulse distortions (Figure 1) can hinder radar target identification.
Various targets modify or modulate the radar echo in unique ways. This information helps algorithms recognize those objects, distinguishing commercial aircraft from military jet fighters, for instance. If the amplifier sends out the RF carrier with a distorted envelope, the ability to reliably determine target velocity, position, and characteristics is diminished.
Addressing pulse degradation
To achieve optimal power, the load and source impedances at the device plane must be designed for peak power. Once the impedance match at RF frequencies has been optimized, the drain-bias circuit should be carefully designed so as not to affect that match. A poorly designed drain bias is often the cause of the power amplifier degrading pulse fidelity.
The basic design philosophy must be that the bias network be as close to ideal as possible. As shown in Figure 2, this is realized by:
Avoiding voltage drop over the bias circuit to apply the maximum power supply voltage at the drain. The DC impedance of the circuit must therefore be close to zero.
Maximizing the RF power going into the load by ensuring the impedance looking from the device up the bias line is infinite (open) at RF frequencies.
Aiming for an ideal representation of the modulating waveform by keeping the impedance of the bias circuit for modulation frequencies — usually 1 kHz to 1 MHz — low. This limits the generation of voltage at modulation frequencies and prevents current and power overshoot and ringing.
Avoiding supply voltage droop during the “on” part of the pulse when the device current demand from the bias circuit is high. This helps maximize RF output power.
Figure 2: Part of an AWR schematic of a microwave PA highlighting the drain-bias circuit design philosophy
It has long been the design community’s accepted practice to add large electrolytic capacitances, followed by capacitors separated by a decade or so in value along the bias line. However, the focus today on extremely high-power density requires careful assessment of necessary electrolytic capacitance and decoupling capacitance values, as well as determination of optimal placement of RF capacitance and any spacing needed between bypass capacitors.
Figure 3: A typical drain-biasing network for an RF PA showing the various components that can affect performance
Choosing RF cap value & placement
Consider the typical drain-biasing network in Figure 3. Moving in a direction away from the drain, the RF capacitor C5 has the smallest capacitance, but its location is the most important.
Working in RF means that capacitor impedance is not simply 1/j(2πfc). Each component has parasitics associated with its package, and the equivalent circuit of a capacitor, for example, has not only its series nominal value but parasitic R, L, and C components that depend on device manufacturing characteristics. Because parasitic reactances change with frequency, it is important to avoid component choices that would result in signal loss.
Figure 4 shows simulation results from analyzing a 36-pF ATC600F capacitor-equivalent circuit model over frequency. To ensure the bias circuit looks like an open at RF, the capacitor must be resonant at the carrier frequency. The 36-pF value in this particular package resonates at the 1.1-GHz carrier frequency. Both charts in Figure 4 are looking into this RF capacitor to ground and show that the impedance decreases with increasing frequency until resonance, after which package parasitics dominate and the impedance rises with frequency as if it were an inductor.
Figure 4: Simulation results of the ATC600F capacitor using highly accurate Modelithics models
The placement of this first capacitor is equally critical. The capacitor must be moved far enough away from the drain and down the bias line so that it looks like an open circuit to the impedance match. Because the electrical length that rotates the original short to an open is a quarter-wave, the RF capacitor is usually placed that distance down the line.
Even capacitor orientation makes a difference. As opposed to mounting a capacitor flat with its internal plates parallel to the RF trace, mounting it vertically with the plates perpendicular to the trace pushes up the resonance frequency.
Intelligent capacitor mixing
Intelligently combining capacitors along the bias line can smoothen the otherwise sharp resonance from the frequency response, thereby keeping the bias network impedance at modulation-type frequencies low and flat.
This helps achieve the design goal: better pulse fidelity.
Sizing electrolytic caps
The desired system size, weight, and power characteristics depend on limiting habitual use of large drain electrolytic capacitors. The minimum capacitance, C, given the maximum IC required and a maximum dV/dt (allowable droop per unit of time) can be calculated using the following equations:
Starting with a proven reference
Figure 5: The CGHV14800F-AMP4 is optimized using techniques discussed here to achieve radar pulse fidelity.
Wolfspeed experts use such techniques to optimize designs by ensuring the drain-bias network contributes to high RF power-out with high pulse fidelity. Wolfspeed’s CGHV14800F-AMP4 demonstration circuit, for instance, offers an extensively tested and proven starting point. Utilizing the CGHV14800F GaN HEMT device, suitable for pulsed L-band radar amplifier applications, the design achieves 800 W in the 1,030- to 1,090-MHz avionics band.
To learn more, read about GaN HEMT Pulsing Circuits and then move on to the webinar on Recommendations for Improving Pulse Fidelity in RF Power Amplifiers to acquire in-depth knowledge about how Wolfspeed engineers determine capacitor values and placements, conduct extensive simulations using highly accurate device models to reduce bench test time, and what phenomena they look for when tuning their circuits for optimal performance.
A radar system designer’s most coveted objectives are achieving a long range, adequate resolution to distinguish objects in close proximity to each other, and the ability to not only determine target velocities but target types in order to help differentiate friendlies from adversaries.A combination of both approaches is essential, and engineers can design for peak power points of the load-pull simulation while also paying attention to other parts of the circuit for baseband signal fidelity.
